1. Field of the Invention
This invention relates to a process for manufacturing multi-level interconnections in integrated circuits for semiconductor devices, and more particularly, to an improved process that reduces interlevel defects when using a reactive ion etch (RIE) to form very small vias.
2. Description of the Prior Art
As illustrated in FIG. 1, one type of prior art multi-layer interconnection of integrated circuits for semiconductor devices has a number of metal levels 10 interconnected by vias/studs 12. In this type of prior art multi-layer metal interconnections are separated by silicon oxide layers 14 (e.g., sputtered quartz, ECR oxide, or PECVD oxide) covered with a passivating oxide layer 16 formed by chemical vapor deposition (PECVD silicon nitride). The via metallization is typically tungsten or aluminum copper and the wiring pattern metallization is typically an alloy, such as an aluminum-copper alloy. A RIE process is used to form vias with a very small feature size.
While generally satisfactory, a significant failure mode in the above-described multilevel interconnection of the integrated circuit is the occurrence of interlevel short circuits. Such shorts may be caused by photolithography misregistration, pinholes in the passivating oxide layer, metal fencing and metal particles. Examples of such defects are shown in FIG. 1 and labeled A, B, C, and D.